Buffering

The card is put in a standard 62-contact XT extension slot. The slot is drawn in the upper left of the diagram.

The data lines SD0-SD7 are buffered by a bidirectional 3-state 74LS245. The buffer direction is determined by the DIR input connected to #math5##tex2html_wrap_inline755#
of the slot. It is from B to A during an I/O read (#math6##tex2html_wrap_inline757#
=DIR low), and from A to B during an I/O write (#math7##tex2html_wrap_inline759#
=DIR low). Both ports are in a high-impedance state (virtually disconnected from the circuit) when their is no access to the card.

The control lines #math8##tex2html_wrap_inline761#
, #math9##tex2html_wrap_inline763#
, RESET and AEN are buffered by the unidirectional 3-state buffer 74LS244. It is always enabled because #math10##tex2html_wrap_inline765#
en #math11##tex2html_wrap_inline767#
are low.

The address lines SA2-SA9 are unbuffered because these are only loaded by the 8-bit 74LS688 comparator. The unbuffered address lines SA0 en SA1 are loaded by 2 Schottky TTL loads each, while a maximum of 1 is recommended. This will cause no problems in general, certainly not when not all extension slots are used.